1. Field of the Invention
The present invention relates to the field of integrated circuit devices, and more specifically, to the design of a bonding pad structure for such devices.
2. Background Information
Integrated circuit chips (dice) are manufactured by fabricating a plurality of identical circuits on a semiconductor wafer, scribing the wafer between the circuits, and subsequently breaking apart the wafer into individual chips. The chips are then mounted on lead frames or substrates for packaging and wire bonded for chip external connections. The bonding wire connects the bonding pads on the chip with the lead frame. IC chips can be bonded using thermocompression or ultrasonic techniques. In thermocompression bonding, heat and pressure are applied to the pad and to the underlying substrate in order to achieve the bond. In ultrasonic bonding, sufficient energy is supplied by ultrasonic vibration to achieve the bond.
Active circuit elements, including transistors, resistors, capacitors, inductors, and the like, are generally located in the central portion of the semiconductor device, while bonding pads have been located around the periphery of the active region on the chip. Bonding pads are generally not located above the active circuits in order to protect the active circuit elements during bonding processes.
In many instances, it may be desirable to place active circuits beneath the bonding pads. For example, it may advantageous to place active circuits under bonding pads in order to decrease die area and to reduce parasitic resistance due to long interconnection wires between bonding pads and active regions. However, due to thermal and mechanical stresses occurring during the bonding process, the underlying circuits may become damaged. For example, as the wire and the die are heated during the process of connecting the wire to the bonding pad, the bonding wire is pressed onto the bonding pad. Additional energy may be supplied by ultrasonic vibration in order to form the bond. When pressure or vibration is exerted upon the bonding pad, the bonding pad can be perforated and the underlying circuits may crack which degrades device performance.
Therefore, what is needed is a method for fabricating a bonding pad structure which allows the placement of active circuits beneath a bonding pad, without damaging or otherwise affecting the performance of the active circuits, and a method that enables the manufacture of semiconductor devices with smaller die sizes.
A method for forming a bonding pad structure over an active circuit of an integrated circuit device is disclosed. A plurality of metal layers are deposited over the active circuit. The uppermost metal layer is patterned and etched to form an array of openings in the metal layer. A dielectric layer is deposited over the uppermost metal layer and over the array of openings in the metal layer. A bonding pad is formed over the dielectric layer.
Additional features and benefits of the present invention will become apparent from the detailed description, figures, and claims set forth below.